1. Field of the Invention
The present invention relates to a semiconductor memory device having a memory cell array divided into a plurality of segments, and having read/write amplifiers disposed for respective segments.
2. Description of the Related Art
In semiconductor memory devices, there have been demands for reduction in fabrication cost and higher speed of operation by decreasing chip area.
FIG. 5 is a schematic block diagram of a prior art synchronous DRAM. FIG. 6 is a schematic block diagram showing a part of FIG. 5.
In FIG. 6, each of local data buses LDB1 and LDB2 and a global data bus GDB is made up of two pairs of complementary signal lines for read and write, or one pair of complementary signal lines in common use for read and write. In a case of the two pairs, a column selection line CSL is made up of a read column selection line and a write column selection line.
For example, when contents of a memory cell 14 in a memory cell array 10 are read, a word line WL is activated to cause a very small change in a voltage of a bit line pair BL depending on the contents of the memory cell 14, and the change is amplified by a sense amplifier 15. Then, the column selection line (CSL) for read or write is activated to turn a column switch 11 on, and the amplified voltage of the bit line pair is transmitted through the local data bus LDB to the local data bus LDB2.
In a read operation, a read amplifier 21 is activated in response to activation of a read enable signal REN, the voltage of the LDB2 is amplified by the read amplifier 21, a resulted voltage is provided through the global data bus GDB to an I/O data buffer circuit 30, and a data signal DATA is externally outputted from the I/O data buffer circuit 30. In a write operation, a write amplifier 22 is activated in response to activation of a write enable signal WEN, the voltage is transmitted in a reverse direction and thereby, data is written on a memory cell 14 selected by an activated word line WL and an activated write column selection line (CSL).
The synchronous DRAM of FIG. 5 is of a multibank architecture, and memory cell arrays of FIG. 6 are provided to respective banks 0 to 3. Each memory cell array is divided into segments 0 to 7 each of which has a plurality of cell columns, and read/write amplifiers 20 are disposed for respective segments.
Referring back to FIG. 6, one segment selection circuit 40 is selected by column address (segment address) signals CA8 to CA6 and their complementary signals *CA8 to *CA6 of the higher order 3 bits outputted from an internal column address generation circuit 51, and the output signal REN or WEN of the segment selection circuit 40 is activated in response to activation of a read timing signal RT or a write timing signal WT from a R/W timing circuit 54.
FIG. 7 is a logic circuit diagram of the segment selection circuit 40.
Either signal CA8 or *CA8 , either signal CA7 or *CA7 and either signal CA6 or *CA6 are provided to a NAND gate 41 depending on a corresponding segment selected by the segment selection circuit 40. For example, in a case of a segment 5, the signals CA8 , *CA7 and CA6 are provided to the NAND gate 41. The signals RT and WT are provided to inverters 42 and 43, respectively. The outputs of the NAND gate 41 and the inverter 42 are provided to a NOR gate 44, and the outputs of the NAND gate 41 and the inverter 43 are provided to a NOR gate 45. The signals REN and WEN are respectively outputted from the NOR gates 44 and 45, respectively.
In a state where the three inputs of the NAND gate 41 are all high, its output is low, and in this state, when the read timing signal RT goes high, the output of the inverter 42 goes low, and the read enable signal REN goes high. Likewise, in a state where the three inputs of the NAND gate 41 are all high, when the write timing signal WT goes high, the write enable signal WEN goes high.
Referring back to FIG. 6, since not only the segment address signals CA8 to CA6, but also the complementary signals thereof are provided for segment selection circuits 40, each segment selection circuit 40 for corresponding segment has the same configuration. But, the number of the signal lines for those is large, the segment selection circuits 40 are arranged in the peripheral circuit area apart from the core circuit. Namely, the segment selection circuit 40 has 5 inputs which is larger in number than 2 outputs, the circuit 40 is arranged in the side of the segment address signals CA8 to CA6 and *CA8 to *CA6 to shorten the 5 input lines and to reduce signal line number in the core circuit.
However, since the signal lines REN and WEN are connected to each read/write amplifier 20, in a case of FIG. 5 for example, comparatively long interconnects amounting to 4.times.7.times.2=56 in number are laid out between the peripheral circuit and the core circuit, thus causing increase in chip area.
With such comparatively long interconnects, not only the edges of the signals REN and WEN are rounded, but also degrees of roundness of the edges are different in every chip, which reduces a timing margin of the signals. Even if buffer gates are inserted in signal lines to decrease the roundness of the edges, since signal propagation delay time of the gates is newly added, operation speed will reduce.